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	shader_decode: Implement FFMA
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				@ -16,7 +16,42 @@ u32 ShaderIR::DecodeFfma(BasicBlock& bb, u32 pc) {
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    const Instruction instr = {program_code[pc]};
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    const auto opcode = OpCode::Decode(instr);
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    UNIMPLEMENTED();
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    UNIMPLEMENTED_IF_MSG(instr.ffma.cc != 0, "FFMA cc not implemented");
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    UNIMPLEMENTED_IF_MSG(instr.ffma.tab5980_0 != 1, "FFMA tab5980_0({}) not implemented",
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                         instr.ffma.tab5980_0.Value()); // Seems to be 1 by default based on SMO
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    UNIMPLEMENTED_IF_MSG(instr.ffma.tab5980_1 != 0, "FFMA tab5980_1({}) not implemented",
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                         instr.ffma.tab5980_1.Value());
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    UNIMPLEMENTED_IF_MSG(instr.generates_cc,
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                         "Condition codes generation in FFMA is not implemented");
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    const Node op_a = GetRegister(instr.gpr8);
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    auto [op_b, op_c] = [&]() -> std::tuple<Node, Node> {
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        switch (opcode->get().GetId()) {
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        case OpCode::Id::FFMA_CR: {
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            return {GetConstBuffer(instr.cbuf34.index, instr.cbuf34.offset),
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                    GetRegister(instr.gpr39)};
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        }
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        case OpCode::Id::FFMA_RR:
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            return {GetRegister(instr.gpr20), GetRegister(instr.gpr39)};
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        case OpCode::Id::FFMA_RC: {
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            return {GetRegister(instr.gpr39),
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                    GetConstBuffer(instr.cbuf34.index, instr.cbuf34.offset)};
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        }
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        case OpCode::Id::FFMA_IMM:
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            return {GetImmediate19(instr), GetRegister(instr.gpr39)};
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        default:
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            UNIMPLEMENTED_MSG("Unhandled FFMA instruction: {}", opcode->get().GetName());
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        }
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    }();
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    op_b = GetOperandAbsNegFloat(op_b, false, instr.ffma.negate_b);
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    op_c = GetOperandAbsNegFloat(op_c, false, instr.ffma.negate_c);
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    Node value = Operation(OperationCode::FFma, PRECISE, op_a, op_b, op_c);
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    value = GetSaturatedFloat(value, instr.alu.saturate_d);
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    SetRegister(bb, instr.gpr0, value);
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    return pc;
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}
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