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				https://git.zaroz.cloud/nintendo-back-up/yuzu/yuzu-mainline.git
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	GPU: Preliminary work for texture decoding.
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				@ -31,6 +31,9 @@ add_library(video_core STATIC
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    renderer_opengl/gl_stream_buffer.h
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					    renderer_opengl/gl_stream_buffer.h
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    renderer_opengl/renderer_opengl.cpp
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					    renderer_opengl/renderer_opengl.cpp
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    renderer_opengl/renderer_opengl.h
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					    renderer_opengl/renderer_opengl.h
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					    textures/decoders.cpp
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					    textures/decoders.h
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					    textures/texture.h
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    utils.h
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					    utils.h
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    video_core.cpp
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					    video_core.cpp
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    video_core.h
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					    video_core.h
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@ -2,8 +2,11 @@
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// Licensed under GPLv2 or any later version
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					// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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					// Refer to the license.txt file included.
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					#include <cinttypes>
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#include "common/assert.h"
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					#include "common/assert.h"
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#include "video_core/engines/maxwell_3d.h"
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					#include "video_core/engines/maxwell_3d.h"
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					#include "video_core/textures/decoders.h"
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					#include "video_core/textures/texture.h"
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namespace Tegra {
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					namespace Tegra {
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namespace Engines {
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					namespace Engines {
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@ -160,6 +163,48 @@ void Maxwell3D::ProcessQueryGet() {
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void Maxwell3D::DrawArrays() {
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					void Maxwell3D::DrawArrays() {
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    LOG_WARNING(HW_GPU, "Game requested a DrawArrays, ignoring");
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					    LOG_WARNING(HW_GPU, "Game requested a DrawArrays, ignoring");
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					    auto& fragment_shader = state.shader_stages[static_cast<size_t>(Regs::ShaderStage::Fragment)];
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					    auto& tex_info_buffer = fragment_shader.const_buffers[regs.tex_cb_index];
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					    ASSERT(tex_info_buffer.enabled && tex_info_buffer.address != 0);
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					    GPUVAddr tic_base_address = regs.tic.TICAddress();
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					    GPUVAddr tex_info_buffer_end = tex_info_buffer.address + tex_info_buffer.size;
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					    for (GPUVAddr current_texture = tex_info_buffer.address + 0x20;
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					         current_texture < tex_info_buffer_end; current_texture += 4) {
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					        Texture::TextureHandle tex_info{
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					            Memory::Read32(memory_manager.PhysicalToVirtualAddress(current_texture))};
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					        if (tex_info.tic_id != 0 || tex_info.tsc_id != 0) {
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					            GPUVAddr tic_address_gpu =
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					                tic_base_address + tex_info.tic_id * sizeof(Texture::TICEntry);
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					            VAddr tic_address_cpu = memory_manager.PhysicalToVirtualAddress(tic_address_gpu);
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					            Texture::TICEntry tic_entry;
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					            Memory::ReadBlock(tic_address_cpu, &tic_entry, sizeof(Texture::TICEntry));
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					            auto r_type = tic_entry.r_type.Value();
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					            auto g_type = tic_entry.g_type.Value();
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					            auto b_type = tic_entry.b_type.Value();
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					            auto a_type = tic_entry.a_type.Value();
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					            // TODO(Subv): Different data types for separate components are not supported
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					            ASSERT(r_type == g_type && r_type == b_type && r_type == a_type);
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					            auto format = tic_entry.format.Value();
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					            auto texture = Texture::DecodeTexture(
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					                memory_manager.PhysicalToVirtualAddress(tic_entry.Address()),
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					                tic_entry.format.Value(), tic_entry.Width(), tic_entry.Height());
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					            LOG_CRITICAL(HW_GPU,
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					                         "Fragment shader using texture TIC %08X TSC %08X at address %016" PRIX64,
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					                         tex_info.tic_id.Value(), tex_info.tsc_id.Value(), tic_entry.Address());
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					        }
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					    }
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}
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					}
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void Maxwell3D::BindTextureInfoBuffer(const std::vector<u32>& parameters) {
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					void Maxwell3D::BindTextureInfoBuffer(const std::vector<u32>& parameters) {
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								src/video_core/textures/decoders.cpp
									
									
									
									
									
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										14
									
								
								src/video_core/textures/decoders.cpp
									
									
									
									
									
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							@ -0,0 +1,14 @@
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					// Copyright 2018 yuzu Emulator Project
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					// Licensed under GPLv2 or any later version
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					// Refer to the license.txt file included.
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					#include "video_core/textures/decoders.h"
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					namespace Tegra {
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					namespace Texture {
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					std::vector<u8> DecodeTexture(VAddr address, TextureFormat format, u32 width, u32 height) {
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					    return {};
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					}
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					}
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					} // namespace Tegra
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								src/video_core/textures/decoders.h
									
									
									
									
									
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										20
									
								
								src/video_core/textures/decoders.h
									
									
									
									
									
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							@ -0,0 +1,20 @@
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					// Copyright 2018 yuzu Emulator Project
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					// Licensed under GPLv2 or any later version
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					// Refer to the license.txt file included.
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					#pragma once
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					#include <vector>
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					#include "common/common_types.h"
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					#include "video_core/textures/texture.h"
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					namespace Tegra {
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					namespace Texture {
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					/**
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					 * Decodes a swizzled texture into a RGBA8888 texture.
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					 */
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					std::vector<u8> DecodeTexture(VAddr address, TextureFormat format, u32 width, u32 height);
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					} // namespace Texture
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					} // namespace Tegra
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								src/video_core/textures/texture.h
									
									
									
									
									
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								src/video_core/textures/texture.h
									
									
									
									
									
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					// Copyright 2018 yuzu Emulator Project
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					// Licensed under GPLv2 or any later version
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					// Refer to the license.txt file included.
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					#pragma once
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					#include "common/bit_field.h"
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					#include "common/common_funcs.h"
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					#include "common/common_types.h"
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					#include "video_core/memory_manager.h"
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					namespace Tegra {
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					namespace Texture {
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					enum class TextureFormat : u32 {
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					    DXT1 = 0x24,
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					};
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					union TextureHandle {
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					    u32 raw;
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					    BitField<0, 20, u32> tic_id;
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					    BitField<20, 12, u32> tsc_id;
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					};
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					struct TICEntry {
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					    union {
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					        u32 raw;
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					        BitField<0, 7, TextureFormat> format;
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					        BitField<7, 3, u32> r_type;
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					        BitField<10, 3, u32> g_type;
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					        BitField<13, 3, u32> b_type;
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					        BitField<16, 3, u32> a_type;
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					    };
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					    u32 address_low;
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					    u16 address_high;
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					    INSERT_PADDING_BYTES(6);
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					    u16 width_minus_1;
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					    INSERT_PADDING_BYTES(2);
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					    u16 height_minus_1;
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					    INSERT_PADDING_BYTES(10);
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					    GPUVAddr Address() const {
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					        return static_cast<GPUVAddr>((static_cast<GPUVAddr>(address_high) << 32) | address_low);
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					    }
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					    u32 Width() const {
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					        return width_minus_1 + 1;
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					    }
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					    u32 Height() const {
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					        return height_minus_1 + 1;
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					    }
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					};
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					static_assert(sizeof(TICEntry) == 0x20, "TICEntry has wrong size");
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					} // namespace Texture
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					} // namespace Tegra
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