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	shader_ir: Add comments on missing instruction.
Also shows Nvidia's address space on comments.
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				| @ -146,15 +146,18 @@ u32 ShaderIR::DecodeInstr(NodeBlock& bb, u32 pc) { | |||||||
| 
 | 
 | ||||||
|     const Instruction instr = {program_code[pc]}; |     const Instruction instr = {program_code[pc]}; | ||||||
|     const auto opcode = OpCode::Decode(instr); |     const auto opcode = OpCode::Decode(instr); | ||||||
|  |     const u32 nv_address = ConvertAddressToNvidiaSpace(pc); | ||||||
| 
 | 
 | ||||||
|     // Decoding failure
 |     // Decoding failure
 | ||||||
|     if (!opcode) { |     if (!opcode) { | ||||||
|         UNIMPLEMENTED_MSG("Unhandled instruction: {0:x}", instr.value); |         UNIMPLEMENTED_MSG("Unhandled instruction: {0:x}", instr.value); | ||||||
|  |         bb.push_back(Comment(fmt::format("{:05x} Unimplemented Shader instruction (0x{:016x})", | ||||||
|  |                                          nv_address, instr.value))); | ||||||
|         return pc + 1; |         return pc + 1; | ||||||
|     } |     } | ||||||
| 
 | 
 | ||||||
|     bb.push_back( |     bb.push_back(Comment( | ||||||
|         Comment(fmt::format("{}: {} (0x{:016x})", pc, opcode->get().GetName(), instr.value))); |         fmt::format("{:05x} {} (0x{:016x})", nv_address, opcode->get().GetName(), instr.value))); | ||||||
| 
 | 
 | ||||||
|     using Tegra::Shader::Pred; |     using Tegra::Shader::Pred; | ||||||
|     UNIMPLEMENTED_IF_MSG(instr.pred.full_pred == Pred::NeverExecute, |     UNIMPLEMENTED_IF_MSG(instr.pred.full_pred == Pred::NeverExecute, | ||||||
|  | |||||||
| @ -127,6 +127,10 @@ public: | |||||||
|         return disable_flow_stack; |         return disable_flow_stack; | ||||||
|     } |     } | ||||||
| 
 | 
 | ||||||
|  |     u32 ConvertAddressToNvidiaSpace(const u32 address) const { | ||||||
|  |         return (address - main_offset) * sizeof(Tegra::Shader::Instruction); | ||||||
|  |     } | ||||||
|  | 
 | ||||||
| private: | private: | ||||||
|     void Decode(); |     void Decode(); | ||||||
| 
 | 
 | ||||||
|  | |||||||
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