mirror of
https://git.zaroz.cloud/nintendo-back-up/yuzu/yuzu-mainline.git
synced 2025-03-21 01:53:15 +00:00
4e57f9d5cf
This allows us to use native SPIR-V instructions without having to manually check for NAN.
464 lines
17 KiB
C++
464 lines
17 KiB
C++
// Copyright 2018 yuzu Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include <algorithm>
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#include <array>
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#include <cmath>
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#include "common/assert.h"
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#include "common/common_types.h"
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#include "common/logging/log.h"
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#include "video_core/engines/shader_bytecode.h"
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#include "video_core/shader/node.h"
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#include "video_core/shader/node_helper.h"
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#include "video_core/shader/registry.h"
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#include "video_core/shader/shader_ir.h"
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namespace VideoCommon::Shader {
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using Tegra::Shader::Attribute;
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using Tegra::Shader::Instruction;
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using Tegra::Shader::IpaMode;
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using Tegra::Shader::Pred;
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using Tegra::Shader::PredCondition;
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using Tegra::Shader::PredOperation;
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using Tegra::Shader::Register;
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ShaderIR::ShaderIR(const ProgramCode& program_code, u32 main_offset, CompilerSettings settings,
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Registry& registry)
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: program_code{program_code}, main_offset{main_offset}, settings{settings}, registry{registry} {
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Decode();
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PostDecode();
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}
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ShaderIR::~ShaderIR() = default;
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Node ShaderIR::GetRegister(Register reg) {
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if (reg != Register::ZeroIndex) {
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used_registers.insert(static_cast<u32>(reg));
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}
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return MakeNode<GprNode>(reg);
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}
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Node ShaderIR::GetCustomVariable(u32 id) {
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return MakeNode<CustomVarNode>(id);
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}
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Node ShaderIR::GetImmediate19(Instruction instr) {
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return Immediate(instr.alu.GetImm20_19());
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}
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Node ShaderIR::GetImmediate32(Instruction instr) {
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return Immediate(instr.alu.GetImm20_32());
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}
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Node ShaderIR::GetConstBuffer(u64 index_, u64 offset_) {
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const auto index = static_cast<u32>(index_);
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const auto offset = static_cast<u32>(offset_);
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used_cbufs.try_emplace(index).first->second.MarkAsUsed(offset);
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return MakeNode<CbufNode>(index, Immediate(offset));
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}
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Node ShaderIR::GetConstBufferIndirect(u64 index_, u64 offset_, Node node) {
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const auto index = static_cast<u32>(index_);
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const auto offset = static_cast<u32>(offset_);
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used_cbufs.try_emplace(index).first->second.MarkAsUsedIndirect();
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Node final_offset = [&] {
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// Attempt to inline constant buffer without a variable offset. This is done to allow
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// tracking LDC calls.
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if (const auto gpr = std::get_if<GprNode>(&*node)) {
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if (gpr->GetIndex() == Register::ZeroIndex) {
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return Immediate(offset);
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}
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}
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return Operation(OperationCode::UAdd, NO_PRECISE, std::move(node), Immediate(offset));
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}();
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return MakeNode<CbufNode>(index, std::move(final_offset));
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}
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Node ShaderIR::GetPredicate(u64 pred_, bool negated) {
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const auto pred = static_cast<Pred>(pred_);
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if (pred != Pred::UnusedIndex && pred != Pred::NeverExecute) {
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used_predicates.insert(pred);
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}
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return MakeNode<PredicateNode>(pred, negated);
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}
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Node ShaderIR::GetPredicate(bool immediate) {
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return GetPredicate(static_cast<u64>(immediate ? Pred::UnusedIndex : Pred::NeverExecute));
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}
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Node ShaderIR::GetInputAttribute(Attribute::Index index, u64 element, Node buffer) {
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MarkAttributeUsage(index, element);
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used_input_attributes.emplace(index);
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return MakeNode<AbufNode>(index, static_cast<u32>(element), std::move(buffer));
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}
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Node ShaderIR::GetPhysicalInputAttribute(Tegra::Shader::Register physical_address, Node buffer) {
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uses_physical_attributes = true;
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return MakeNode<AbufNode>(GetRegister(physical_address), buffer);
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}
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Node ShaderIR::GetOutputAttribute(Attribute::Index index, u64 element, Node buffer) {
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MarkAttributeUsage(index, element);
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used_output_attributes.insert(index);
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return MakeNode<AbufNode>(index, static_cast<u32>(element), std::move(buffer));
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}
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Node ShaderIR::GetInternalFlag(InternalFlag flag, bool negated) const {
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const Node node = MakeNode<InternalFlagNode>(flag);
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if (negated) {
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return Operation(OperationCode::LogicalNegate, node);
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}
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return node;
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}
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Node ShaderIR::GetLocalMemory(Node address) {
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return MakeNode<LmemNode>(std::move(address));
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}
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Node ShaderIR::GetSharedMemory(Node address) {
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return MakeNode<SmemNode>(std::move(address));
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}
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Node ShaderIR::GetTemporary(u32 id) {
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return GetRegister(Register::ZeroIndex + 1 + id);
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}
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Node ShaderIR::GetOperandAbsNegFloat(Node value, bool absolute, bool negate) {
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if (absolute) {
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value = Operation(OperationCode::FAbsolute, NO_PRECISE, std::move(value));
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}
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if (negate) {
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value = Operation(OperationCode::FNegate, NO_PRECISE, std::move(value));
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}
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return value;
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}
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Node ShaderIR::GetSaturatedFloat(Node value, bool saturate) {
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if (!saturate) {
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return value;
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}
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Node positive_zero = Immediate(std::copysignf(0, 1));
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Node positive_one = Immediate(1.0f);
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return Operation(OperationCode::FClamp, NO_PRECISE, std::move(value), std::move(positive_zero),
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std::move(positive_one));
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}
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Node ShaderIR::ConvertIntegerSize(Node value, Register::Size size, bool is_signed) {
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switch (size) {
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case Register::Size::Byte:
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value = SignedOperation(OperationCode::ILogicalShiftLeft, is_signed, NO_PRECISE,
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std::move(value), Immediate(24));
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value = SignedOperation(OperationCode::IArithmeticShiftRight, is_signed, NO_PRECISE,
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std::move(value), Immediate(24));
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return value;
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case Register::Size::Short:
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value = SignedOperation(OperationCode::ILogicalShiftLeft, is_signed, NO_PRECISE,
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std::move(value), Immediate(16));
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value = SignedOperation(OperationCode::IArithmeticShiftRight, is_signed, NO_PRECISE,
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std::move(value), Immediate(16));
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return value;
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case Register::Size::Word:
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// Default - do nothing
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return value;
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default:
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UNREACHABLE_MSG("Unimplemented conversion size: {}", static_cast<u32>(size));
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return value;
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}
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}
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Node ShaderIR::GetOperandAbsNegInteger(Node value, bool absolute, bool negate, bool is_signed) {
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if (!is_signed) {
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// Absolute or negate on an unsigned is pointless
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return value;
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}
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if (absolute) {
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value = Operation(OperationCode::IAbsolute, NO_PRECISE, std::move(value));
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}
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if (negate) {
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value = Operation(OperationCode::INegate, NO_PRECISE, std::move(value));
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}
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return value;
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}
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Node ShaderIR::UnpackHalfImmediate(Instruction instr, bool has_negation) {
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Node value = Immediate(instr.half_imm.PackImmediates());
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if (!has_negation) {
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return value;
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}
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Node first_negate = GetPredicate(instr.half_imm.first_negate != 0);
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Node second_negate = GetPredicate(instr.half_imm.second_negate != 0);
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return Operation(OperationCode::HNegate, NO_PRECISE, std::move(value), std::move(first_negate),
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std::move(second_negate));
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}
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Node ShaderIR::UnpackHalfFloat(Node value, Tegra::Shader::HalfType type) {
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return Operation(OperationCode::HUnpack, type, std::move(value));
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}
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Node ShaderIR::HalfMerge(Node dest, Node src, Tegra::Shader::HalfMerge merge) {
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switch (merge) {
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case Tegra::Shader::HalfMerge::H0_H1:
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return src;
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case Tegra::Shader::HalfMerge::F32:
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return Operation(OperationCode::HMergeF32, std::move(src));
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case Tegra::Shader::HalfMerge::Mrg_H0:
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return Operation(OperationCode::HMergeH0, std::move(dest), std::move(src));
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case Tegra::Shader::HalfMerge::Mrg_H1:
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return Operation(OperationCode::HMergeH1, std::move(dest), std::move(src));
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}
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UNREACHABLE();
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return src;
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}
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Node ShaderIR::GetOperandAbsNegHalf(Node value, bool absolute, bool negate) {
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if (absolute) {
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value = Operation(OperationCode::HAbsolute, NO_PRECISE, std::move(value));
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}
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if (negate) {
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value = Operation(OperationCode::HNegate, NO_PRECISE, std::move(value), GetPredicate(true),
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GetPredicate(true));
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}
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return value;
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}
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Node ShaderIR::GetSaturatedHalfFloat(Node value, bool saturate) {
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if (!saturate) {
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return value;
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}
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Node positive_zero = Immediate(std::copysignf(0, 1));
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Node positive_one = Immediate(1.0f);
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return Operation(OperationCode::HClamp, NO_PRECISE, std::move(value), std::move(positive_zero),
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std::move(positive_one));
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}
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Node ShaderIR::GetPredicateComparisonFloat(PredCondition condition, Node op_a, Node op_b) {
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if (condition == PredCondition::T) {
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return GetPredicate(true);
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} else if (condition == PredCondition::F) {
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return GetPredicate(false);
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}
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static constexpr std::array comparison_table{
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OperationCode(0),
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OperationCode::LogicalFOrdLessThan, // LT
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OperationCode::LogicalFOrdEqual, // EQ
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OperationCode::LogicalFOrdLessEqual, // LE
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OperationCode::LogicalFOrdGreaterThan, // GT
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OperationCode::LogicalFOrdNotEqual, // NE
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OperationCode::LogicalFOrdGreaterEqual, // GE
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OperationCode::LogicalFOrdered, // NUM
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OperationCode::LogicalFUnordered, // NAN
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OperationCode::LogicalFUnordLessThan, // LTU
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OperationCode::LogicalFUnordEqual, // EQU
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OperationCode::LogicalFUnordLessEqual, // LEU
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OperationCode::LogicalFUnordGreaterThan, // GTU
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OperationCode::LogicalFUnordNotEqual, // NEU
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OperationCode::LogicalFUnordGreaterEqual, // GEU
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};
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const std::size_t index = static_cast<std::size_t>(condition);
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ASSERT_MSG(index < std::size(comparison_table), "Invalid condition={}", index);
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return Operation(comparison_table[index], op_a, op_b);
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}
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Node ShaderIR::GetPredicateComparisonInteger(PredCondition condition, bool is_signed, Node op_a,
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Node op_b) {
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static constexpr std::array comparison_table{
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std::pair{PredCondition::LT, OperationCode::LogicalILessThan},
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std::pair{PredCondition::EQ, OperationCode::LogicalIEqual},
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std::pair{PredCondition::LE, OperationCode::LogicalILessEqual},
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std::pair{PredCondition::GT, OperationCode::LogicalIGreaterThan},
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std::pair{PredCondition::NE, OperationCode::LogicalINotEqual},
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std::pair{PredCondition::GE, OperationCode::LogicalIGreaterEqual},
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};
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const auto comparison =
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std::find_if(comparison_table.cbegin(), comparison_table.cend(),
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[condition](const auto entry) { return condition == entry.first; });
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UNIMPLEMENTED_IF_MSG(comparison == comparison_table.cend(),
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"Unknown predicate comparison operation");
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return SignedOperation(comparison->second, is_signed, NO_PRECISE, std::move(op_a),
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std::move(op_b));
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}
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Node ShaderIR::GetPredicateComparisonHalf(Tegra::Shader::PredCondition condition, Node op_a,
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Node op_b) {
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static constexpr std::array comparison_table{
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std::pair{PredCondition::LT, OperationCode::Logical2HLessThan},
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std::pair{PredCondition::EQ, OperationCode::Logical2HEqual},
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std::pair{PredCondition::LE, OperationCode::Logical2HLessEqual},
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std::pair{PredCondition::GT, OperationCode::Logical2HGreaterThan},
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std::pair{PredCondition::NE, OperationCode::Logical2HNotEqual},
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std::pair{PredCondition::GE, OperationCode::Logical2HGreaterEqual},
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std::pair{PredCondition::LTU, OperationCode::Logical2HLessThanWithNan},
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std::pair{PredCondition::LEU, OperationCode::Logical2HLessEqualWithNan},
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std::pair{PredCondition::GTU, OperationCode::Logical2HGreaterThanWithNan},
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std::pair{PredCondition::NEU, OperationCode::Logical2HNotEqualWithNan},
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std::pair{PredCondition::GEU, OperationCode::Logical2HGreaterEqualWithNan},
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};
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const auto comparison =
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std::find_if(comparison_table.cbegin(), comparison_table.cend(),
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[condition](const auto entry) { return condition == entry.first; });
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UNIMPLEMENTED_IF_MSG(comparison == comparison_table.cend(),
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"Unknown predicate comparison operation");
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return Operation(comparison->second, NO_PRECISE, std::move(op_a), std::move(op_b));
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}
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OperationCode ShaderIR::GetPredicateCombiner(PredOperation operation) {
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static constexpr std::array operation_table{
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OperationCode::LogicalAnd,
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OperationCode::LogicalOr,
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OperationCode::LogicalXor,
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};
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const auto index = static_cast<std::size_t>(operation);
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if (index >= operation_table.size()) {
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UNIMPLEMENTED_MSG("Unknown predicate operation.");
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return {};
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}
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return operation_table[index];
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}
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Node ShaderIR::GetConditionCode(Tegra::Shader::ConditionCode cc) const {
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switch (cc) {
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case Tegra::Shader::ConditionCode::NEU:
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return GetInternalFlag(InternalFlag::Zero, true);
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case Tegra::Shader::ConditionCode::FCSM_TR:
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UNIMPLEMENTED_MSG("EXIT.FCSM_TR is not implemented");
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return MakeNode<PredicateNode>(Pred::NeverExecute, false);
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default:
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UNIMPLEMENTED_MSG("Unimplemented condition code: {}", static_cast<u32>(cc));
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return MakeNode<PredicateNode>(Pred::NeverExecute, false);
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}
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}
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void ShaderIR::SetRegister(NodeBlock& bb, Register dest, Node src) {
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bb.push_back(Operation(OperationCode::Assign, GetRegister(dest), std::move(src)));
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}
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void ShaderIR::SetPredicate(NodeBlock& bb, u64 dest, Node src) {
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bb.push_back(Operation(OperationCode::LogicalAssign, GetPredicate(dest), std::move(src)));
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}
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void ShaderIR::SetInternalFlag(NodeBlock& bb, InternalFlag flag, Node value) {
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bb.push_back(Operation(OperationCode::LogicalAssign, GetInternalFlag(flag), std::move(value)));
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}
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void ShaderIR::SetLocalMemory(NodeBlock& bb, Node address, Node value) {
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bb.push_back(
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Operation(OperationCode::Assign, GetLocalMemory(std::move(address)), std::move(value)));
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}
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void ShaderIR::SetSharedMemory(NodeBlock& bb, Node address, Node value) {
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bb.push_back(
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Operation(OperationCode::Assign, GetSharedMemory(std::move(address)), std::move(value)));
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}
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void ShaderIR::SetTemporary(NodeBlock& bb, u32 id, Node value) {
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SetRegister(bb, Register::ZeroIndex + 1 + id, std::move(value));
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}
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void ShaderIR::SetInternalFlagsFromFloat(NodeBlock& bb, Node value, bool sets_cc) {
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if (!sets_cc) {
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return;
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}
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Node zerop = Operation(OperationCode::LogicalFOrdEqual, std::move(value), Immediate(0.0f));
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SetInternalFlag(bb, InternalFlag::Zero, std::move(zerop));
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LOG_WARNING(HW_GPU, "Condition codes implementation is incomplete");
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}
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void ShaderIR::SetInternalFlagsFromInteger(NodeBlock& bb, Node value, bool sets_cc) {
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if (!sets_cc) {
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return;
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}
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Node zerop = Operation(OperationCode::LogicalIEqual, std::move(value), Immediate(0));
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SetInternalFlag(bb, InternalFlag::Zero, std::move(zerop));
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LOG_WARNING(HW_GPU, "Condition codes implementation is incomplete");
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}
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Node ShaderIR::BitfieldExtract(Node value, u32 offset, u32 bits) {
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return Operation(OperationCode::UBitfieldExtract, NO_PRECISE, std::move(value),
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Immediate(offset), Immediate(bits));
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}
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Node ShaderIR::BitfieldInsert(Node base, Node insert, u32 offset, u32 bits) {
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return Operation(OperationCode::UBitfieldInsert, NO_PRECISE, base, insert, Immediate(offset),
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Immediate(bits));
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}
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void ShaderIR::MarkAttributeUsage(Attribute::Index index, u64 element) {
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switch (index) {
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case Attribute::Index::LayerViewportPointSize:
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switch (element) {
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case 0:
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UNIMPLEMENTED();
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break;
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case 1:
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uses_layer = true;
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break;
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case 2:
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uses_viewport_index = true;
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break;
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case 3:
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uses_point_size = true;
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break;
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}
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break;
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case Attribute::Index::TessCoordInstanceIDVertexID:
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switch (element) {
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case 2:
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uses_instance_id = true;
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break;
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case 3:
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uses_vertex_id = true;
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break;
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}
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break;
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case Attribute::Index::ClipDistances0123:
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case Attribute::Index::ClipDistances4567: {
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const u64 clip_index = (index == Attribute::Index::ClipDistances4567 ? 4 : 0) + element;
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used_clip_distances.at(clip_index) = true;
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break;
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}
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case Attribute::Index::FrontColor:
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case Attribute::Index::FrontSecondaryColor:
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case Attribute::Index::BackColor:
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case Attribute::Index::BackSecondaryColor:
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uses_legacy_varyings = true;
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break;
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default:
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if (index >= Attribute::Index::TexCoord_0 && index <= Attribute::Index::TexCoord_7) {
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uses_legacy_varyings = true;
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}
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break;
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}
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}
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std::size_t ShaderIR::DeclareAmend(Node new_amend) {
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const std::size_t id = amend_code.size();
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amend_code.push_back(new_amend);
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return id;
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}
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u32 ShaderIR::NewCustomVariable() {
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return num_custom_variables++;
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}
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} // namespace VideoCommon::Shader
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