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	GSP_GPU: Remove use of Memory::GetPointer
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				@ -65,15 +65,27 @@ static inline InterruptRelayQueue* GetInterruptRelayQueue(u32 thread_id) {
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    return reinterpret_cast<InterruptRelayQueue*>(ptr);
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}
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/**
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 * Writes a single GSP GPU hardware registers with a single u32 value
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 * (For internal use.)
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 *
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 * @param base_address The address of the register in question
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 * @param data Data to be written
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 */
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static void WriteSingleHWReg(u32 base_address, u32 data) {
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    DEBUG_ASSERT_MSG((base_address & 3) == 0 && base_address < 0x420000, "Write address out of range or misaligned");
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    HW::Write<u32>(base_address + REGS_BEGIN, data);
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}
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/**
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 * Writes sequential GSP GPU hardware registers using an array of source data
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 *
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 * @param base_address The address of the first register in the sequence
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 * @param size_in_bytes The number of registers to update (size of data)
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 * @param data A pointer to the source data
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 * @param data_vaddr A pointer to the source data
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 * @return RESULT_SUCCESS if the parameters are valid, error code otherwise
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 */
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static ResultCode WriteHWRegs(u32 base_address, u32 size_in_bytes, const u32* data) {
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static ResultCode WriteHWRegs(u32 base_address, u32 size_in_bytes, VAddr data_vaddr) {
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    // This magic number is verified to be done by the gsp module
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    const u32 max_size_in_bytes = 0x80;
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@ -87,10 +99,10 @@ static ResultCode WriteHWRegs(u32 base_address, u32 size_in_bytes, const u32* da
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            return ERR_GSP_REGS_MISALIGNED;
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        } else {
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            while (size_in_bytes > 0) {
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                HW::Write<u32>(base_address + REGS_BEGIN, *data);
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                WriteSingleHWReg(base_address, Memory::Read32(data_vaddr));
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                size_in_bytes -= 4;
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                ++data;
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                data_vaddr += 4;
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                base_address += 4;
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            }
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            return RESULT_SUCCESS;
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@ -112,7 +124,7 @@ static ResultCode WriteHWRegs(u32 base_address, u32 size_in_bytes, const u32* da
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 * @param masks A pointer to the masks
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 * @return RESULT_SUCCESS if the parameters are valid, error code otherwise
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 */
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static ResultCode WriteHWRegsWithMask(u32 base_address, u32 size_in_bytes, const u32* data, const u32* masks) {
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static ResultCode WriteHWRegsWithMask(u32 base_address, u32 size_in_bytes, VAddr data_vaddr, VAddr masks_vaddr) {
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    // This magic number is verified to be done by the gsp module
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    const u32 max_size_in_bytes = 0x80;
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@ -131,14 +143,17 @@ static ResultCode WriteHWRegsWithMask(u32 base_address, u32 size_in_bytes, const
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                u32 reg_value;
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                HW::Read<u32>(reg_value, reg_address);
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                // Update the current value of the register only for set mask bits
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                reg_value = (reg_value & ~*masks) | (*data | *masks);
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                u32 data = Memory::Read32(data_vaddr);
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                u32 mask = Memory::Read32(masks_vaddr);
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                HW::Write<u32>(reg_address, reg_value);
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                // Update the current value of the register only for set mask bits
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                reg_value = (reg_value & ~mask) | (data | mask);
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                WriteSingleHWReg(base_address, reg_value);
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                size_in_bytes -= 4;
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                ++data;
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                ++masks;
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                data_vaddr += 4;
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                masks_vaddr += 4;
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                base_address += 4;
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            }
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            return RESULT_SUCCESS;
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@ -164,8 +179,7 @@ static void WriteHWRegs(Service::Interface* self) {
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    u32* cmd_buff = Kernel::GetCommandBuffer();
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    u32 reg_addr = cmd_buff[1];
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    u32 size = cmd_buff[2];
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    u32* src = (u32*)Memory::GetPointer(cmd_buff[4]);
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    VAddr src = cmd_buff[4];
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    cmd_buff[1] = WriteHWRegs(reg_addr, size, src).raw;
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}
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@ -186,8 +200,8 @@ static void WriteHWRegsWithMask(Service::Interface* self) {
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    u32 reg_addr = cmd_buff[1];
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    u32 size = cmd_buff[2];
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    u32* src_data = (u32*)Memory::GetPointer(cmd_buff[4]);
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    u32* mask_data = (u32*)Memory::GetPointer(cmd_buff[6]);
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    VAddr src_data = cmd_buff[4];
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    VAddr mask_data = cmd_buff[6];
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    cmd_buff[1] = WriteHWRegsWithMask(reg_addr, size, src_data, mask_data).raw;
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}
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@ -210,13 +224,16 @@ static void ReadHWRegs(Service::Interface* self) {
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        return;
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    }
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    u32* dst = (u32*)Memory::GetPointer(cmd_buff[0x41]);
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    VAddr dst_vaddr = cmd_buff[0x41];
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    while (size > 0) {
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        HW::Read<u32>(*dst, reg_addr + REGS_BEGIN);
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        u32 value;
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        HW::Read<u32>(value, reg_addr + REGS_BEGIN);
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        Memory::Write32(dst_vaddr, value);
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        size -= 4;
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        ++dst;
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        dst_vaddr += 4;
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        reg_addr += 4;
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    }
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}
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@ -226,22 +243,22 @@ ResultCode SetBufferSwap(u32 screen_id, const FrameBufferInfo& info) {
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    PAddr phys_address_left = Memory::VirtualToPhysicalAddress(info.address_left);
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    PAddr phys_address_right = Memory::VirtualToPhysicalAddress(info.address_right);
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    if (info.active_fb == 0) {
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        WriteHWRegs(base_address + 4 * static_cast<u32>(GPU_REG_INDEX(framebuffer_config[screen_id].address_left1)),
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                    4, &phys_address_left);
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        WriteHWRegs(base_address + 4 * static_cast<u32>(GPU_REG_INDEX(framebuffer_config[screen_id].address_right1)),
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                    4, &phys_address_right);
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        WriteSingleHWReg(base_address + 4 * static_cast<u32>(GPU_REG_INDEX(framebuffer_config[screen_id].address_left1)),
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                         phys_address_left);
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        WriteSingleHWReg(base_address + 4 * static_cast<u32>(GPU_REG_INDEX(framebuffer_config[screen_id].address_right1)),
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                         phys_address_right);
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    } else {
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        WriteHWRegs(base_address + 4 * static_cast<u32>(GPU_REG_INDEX(framebuffer_config[screen_id].address_left2)),
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                    4, &phys_address_left);
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        WriteHWRegs(base_address + 4 * static_cast<u32>(GPU_REG_INDEX(framebuffer_config[screen_id].address_right2)),
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                    4, &phys_address_right);
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        WriteSingleHWReg(base_address + 4 * static_cast<u32>(GPU_REG_INDEX(framebuffer_config[screen_id].address_left2)),
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                         phys_address_left);
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        WriteSingleHWReg(base_address + 4 * static_cast<u32>(GPU_REG_INDEX(framebuffer_config[screen_id].address_right2)),
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                         phys_address_right);
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    }
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    WriteHWRegs(base_address + 4 * static_cast<u32>(GPU_REG_INDEX(framebuffer_config[screen_id].stride)),
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                4, &info.stride);
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    WriteHWRegs(base_address + 4 * static_cast<u32>(GPU_REG_INDEX(framebuffer_config[screen_id].color_format)),
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                4, &info.format);
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    WriteHWRegs(base_address + 4 * static_cast<u32>(GPU_REG_INDEX(framebuffer_config[screen_id].active_fb)),
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                4, &info.shown_fb);
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    WriteSingleHWReg(base_address + 4 * static_cast<u32>(GPU_REG_INDEX(framebuffer_config[screen_id].stride)),
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                     info.stride);
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    WriteSingleHWReg(base_address + 4 * static_cast<u32>(GPU_REG_INDEX(framebuffer_config[screen_id].color_format)),
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                     info.format);
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    WriteSingleHWReg(base_address + 4 * static_cast<u32>(GPU_REG_INDEX(framebuffer_config[screen_id].active_fb)),
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                     info.shown_fb);
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    if (Pica::g_debug_context)
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        Pica::g_debug_context->OnEvent(Pica::DebugContext::Event::BufferSwapped, nullptr);
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@ -432,9 +449,9 @@ static void ExecuteCommand(const Command& command, u32 thread_id) {
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        Memory::RasterizerFlushAndInvalidateRegion(Memory::VirtualToPhysicalAddress(command.dma_request.dest_address),
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                            command.dma_request.size);
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        memcpy(Memory::GetPointer(command.dma_request.dest_address),
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               Memory::GetPointer(command.dma_request.source_address),
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               command.dma_request.size);
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        // TODO(Subv): These memory accesses should not go through the application's memory mapping.
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        // They should go through the GSP module's memory mapping.
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        Memory::CopyBlock(command.dma_request.dest_address, command.dma_request.source_address, command.dma_request.size);
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        SignalInterrupt(InterruptId::DMA);
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        break;
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    }
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